The trends and technology towards miniaturization of integrated circuits is outpacing the technology for packaging such integrated circuits. For instance, very fine pitched leaded components and surface mounted devices (SMD's) are very difficult to solder onto printed circuit boards or printed wiring boards without a significant number of defects. Current practical lead pitch barriers of a approximately 25 mils exists with conventional solder print, place, and reflow technologies due to a high joint defect level (over 25 defective parts per million joints). Several factors, including solder paste rheology, printing machine controls, solder stencil aperture sizes and side wall characteristics, and volume of solder per pad variations contribute towards this barrier.
The cause of such a high joint defect rate is also attributable to the lack of a method to precisely control the solder volume per substrate solder pad and the lack of a uniform height of solder on the substrate solder pad with collapsible characteristics during reflow to fine pitched leads. Existing methods of applying solder such as screen printing fails to provide a sufficiently controllable solder volume and height due to variations in the percentage of solids in the solder paste and offset stencils that are slightly misaligned with the solder pads. Shorts between leads on adjacent solder pads are also created when component leads are set down onto solder. Other methods such as plating solder onto substrates presents the problem of controlling the optimum ratio of tin to lead. Additionally, if the printed circuit boards used are of a mixed technology (for instance one side of a substrate can be screen printed and reflowed while the opposing side can be wave soldered), fine pitched devices can only be interconnected using expensive solder plating from the printed circuit board vendor using superior control over solder printing operations and solder paste. Thus, a need exists for a easily implementable process and apparatus that would facilitate the formation of solder interconnects between surface mounted components and very finely pitched leaded components to electrical substrates with superior soldering yields and which further overcome the problems stated above.